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99ceb03a1c
This formats all copyright comments according to SPDX formatting guidelines. Additionally, this resolves the remaining GPLv2 only licensed files by relicensing them to GPLv2.0-or-later.
236 lines
7.2 KiB
C++
236 lines
7.2 KiB
C++
// SPDX-FileCopyrightText: Copyright 2021 yuzu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include <optional>
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/ir/modifiers.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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enum class Blod : u64 {
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None,
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LZ,
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LB,
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LL,
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INVALIDBLOD4,
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INVALIDBLOD5,
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LBA,
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LLA,
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};
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enum class TextureType : u64 {
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_1D,
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ARRAY_1D,
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_2D,
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ARRAY_2D,
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_3D,
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ARRAY_3D,
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CUBE,
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ARRAY_CUBE,
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};
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Shader::TextureType GetType(TextureType type) {
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switch (type) {
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case TextureType::_1D:
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return Shader::TextureType::Color1D;
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case TextureType::ARRAY_1D:
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return Shader::TextureType::ColorArray1D;
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case TextureType::_2D:
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return Shader::TextureType::Color2D;
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case TextureType::ARRAY_2D:
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return Shader::TextureType::ColorArray2D;
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case TextureType::_3D:
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return Shader::TextureType::Color3D;
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case TextureType::ARRAY_3D:
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throw NotImplementedException("3D array texture type");
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case TextureType::CUBE:
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return Shader::TextureType::ColorCube;
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case TextureType::ARRAY_CUBE:
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return Shader::TextureType::ColorArrayCube;
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}
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throw NotImplementedException("Invalid texture type {}", type);
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}
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IR::Value MakeCoords(TranslatorVisitor& v, IR::Reg reg, TextureType type) {
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const auto read_array{[&]() -> IR::F32 { return v.ir.ConvertUToF(32, 16, v.X(reg)); }};
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switch (type) {
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case TextureType::_1D:
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return v.F(reg);
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case TextureType::ARRAY_1D:
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return v.ir.CompositeConstruct(v.F(reg + 1), read_array());
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case TextureType::_2D:
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return v.ir.CompositeConstruct(v.F(reg), v.F(reg + 1));
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case TextureType::ARRAY_2D:
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return v.ir.CompositeConstruct(v.F(reg + 1), v.F(reg + 2), read_array());
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case TextureType::_3D:
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return v.ir.CompositeConstruct(v.F(reg), v.F(reg + 1), v.F(reg + 2));
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case TextureType::ARRAY_3D:
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throw NotImplementedException("3D array texture type");
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case TextureType::CUBE:
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return v.ir.CompositeConstruct(v.F(reg), v.F(reg + 1), v.F(reg + 2));
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case TextureType::ARRAY_CUBE:
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return v.ir.CompositeConstruct(v.F(reg + 1), v.F(reg + 2), v.F(reg + 3), read_array());
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}
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throw NotImplementedException("Invalid texture type {}", type);
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}
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IR::F32 MakeLod(TranslatorVisitor& v, IR::Reg& reg, Blod blod) {
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switch (blod) {
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case Blod::None:
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return v.ir.Imm32(0.0f);
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case Blod::LZ:
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return v.ir.Imm32(0.0f);
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case Blod::LB:
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case Blod::LL:
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case Blod::LBA:
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case Blod::LLA:
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return v.F(reg++);
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case Blod::INVALIDBLOD4:
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case Blod::INVALIDBLOD5:
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break;
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}
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throw NotImplementedException("Invalid blod {}", blod);
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}
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IR::Value MakeOffset(TranslatorVisitor& v, IR::Reg& reg, TextureType type) {
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const IR::U32 value{v.X(reg++)};
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switch (type) {
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case TextureType::_1D:
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case TextureType::ARRAY_1D:
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return v.ir.BitFieldExtract(value, v.ir.Imm32(0), v.ir.Imm32(4), true);
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case TextureType::_2D:
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case TextureType::ARRAY_2D:
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return v.ir.CompositeConstruct(
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v.ir.BitFieldExtract(value, v.ir.Imm32(0), v.ir.Imm32(4), true),
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v.ir.BitFieldExtract(value, v.ir.Imm32(4), v.ir.Imm32(4), true));
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case TextureType::_3D:
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case TextureType::ARRAY_3D:
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return v.ir.CompositeConstruct(
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v.ir.BitFieldExtract(value, v.ir.Imm32(0), v.ir.Imm32(4), true),
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v.ir.BitFieldExtract(value, v.ir.Imm32(4), v.ir.Imm32(4), true),
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v.ir.BitFieldExtract(value, v.ir.Imm32(8), v.ir.Imm32(4), true));
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case TextureType::CUBE:
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case TextureType::ARRAY_CUBE:
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throw NotImplementedException("Illegal offset on CUBE sample");
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}
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throw NotImplementedException("Invalid texture type {}", type);
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}
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bool HasExplicitLod(Blod blod) {
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switch (blod) {
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case Blod::LL:
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case Blod::LLA:
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case Blod::LZ:
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return true;
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default:
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return false;
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}
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}
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void Impl(TranslatorVisitor& v, u64 insn, bool aoffi, Blod blod, bool lc,
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std::optional<u32> cbuf_offset) {
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union {
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u64 raw;
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BitField<35, 1, u64> ndv;
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BitField<49, 1, u64> nodep;
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BitField<50, 1, u64> dc;
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BitField<51, 3, IR::Pred> sparse_pred;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<8, 8, IR::Reg> coord_reg;
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BitField<20, 8, IR::Reg> meta_reg;
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BitField<28, 3, TextureType> type;
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BitField<31, 4, u64> mask;
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} const tex{insn};
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if (lc) {
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throw NotImplementedException("LC");
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}
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const IR::Value coords{MakeCoords(v, tex.coord_reg, tex.type)};
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IR::Reg meta_reg{tex.meta_reg};
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IR::Value handle;
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IR::Value offset;
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IR::F32 dref;
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IR::F32 lod_clamp;
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if (cbuf_offset) {
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handle = v.ir.Imm32(*cbuf_offset);
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} else {
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handle = v.X(meta_reg++);
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}
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const IR::F32 lod{MakeLod(v, meta_reg, blod)};
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if (aoffi) {
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offset = MakeOffset(v, meta_reg, tex.type);
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}
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if (tex.dc != 0) {
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dref = v.F(meta_reg++);
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}
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IR::TextureInstInfo info{};
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info.type.Assign(GetType(tex.type));
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info.is_depth.Assign(tex.dc != 0 ? 1 : 0);
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info.has_bias.Assign(blod == Blod::LB || blod == Blod::LBA ? 1 : 0);
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info.has_lod_clamp.Assign(lc ? 1 : 0);
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const IR::Value sample{[&]() -> IR::Value {
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if (tex.dc == 0) {
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if (HasExplicitLod(blod)) {
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return v.ir.ImageSampleExplicitLod(handle, coords, lod, offset, info);
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} else {
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return v.ir.ImageSampleImplicitLod(handle, coords, lod, offset, lod_clamp, info);
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}
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}
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if (HasExplicitLod(blod)) {
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return v.ir.ImageSampleDrefExplicitLod(handle, coords, dref, lod, offset, info);
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} else {
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return v.ir.ImageSampleDrefImplicitLod(handle, coords, dref, lod, offset, lod_clamp,
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info);
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}
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}()};
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IR::Reg dest_reg{tex.dest_reg};
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for (int element = 0; element < 4; ++element) {
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if (((tex.mask >> element) & 1) == 0) {
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continue;
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}
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IR::F32 value;
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if (tex.dc != 0) {
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value = element < 3 ? IR::F32{sample} : v.ir.Imm32(1.0f);
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} else {
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value = IR::F32{v.ir.CompositeExtract(sample, static_cast<size_t>(element))};
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}
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v.F(dest_reg, value);
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++dest_reg;
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}
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if (tex.sparse_pred != IR::Pred::PT) {
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v.ir.SetPred(tex.sparse_pred, v.ir.LogicalNot(v.ir.GetSparseFromOp(sample)));
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}
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}
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} // Anonymous namespace
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void TranslatorVisitor::TEX(u64 insn) {
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union {
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u64 raw;
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BitField<54, 1, u64> aoffi;
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BitField<55, 3, Blod> blod;
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BitField<58, 1, u64> lc;
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BitField<36, 13, u64> cbuf_offset;
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} const tex{insn};
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Impl(*this, insn, tex.aoffi != 0, tex.blod, tex.lc != 0, static_cast<u32>(tex.cbuf_offset * 4));
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}
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void TranslatorVisitor::TEX_b(u64 insn) {
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union {
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u64 raw;
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BitField<36, 1, u64> aoffi;
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BitField<37, 3, Blod> blod;
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BitField<40, 1, u64> lc;
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} const tex{insn};
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Impl(*this, insn, tex.aoffi != 0, tex.blod, tex.lc != 0, std::nullopt);
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}
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} // namespace Shader::Maxwell
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