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ryujinx/ARMeilleure/Decoders
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Mary 501c3d5cea
Implement MSR instruction for A32 (#2585) 
* Implement MSR instruction

Fix #1342.

Now Pocket Rumble is playable.

* Address gdkchan's comments

* Address gdkchan's comments

* Address gdkchan's comment
2021-08-27 00:07:44 +02:00
..
Optimizations
Add inlined on translation call counting (#2190)
2021-04-18 23:43:53 +02:00
Block.cs
Add inlined on translation call counting (#2190)
2021-04-18 23:43:53 +02:00
Condition.cs
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DataOp.cs
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Decoder.cs
PPTC Follow-up. (#1712)
2020-12-17 20:32:09 +01:00
DecoderHelper.cs
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InstDescriptor.cs
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InstEmitter.cs
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IntType.cs
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IOpCode32.cs
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IOpCode32Alu.cs
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IOpCode32AluBf.cs
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IOpCode32AluReg.cs
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IOpCode32AluUx.cs
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IOpCode32BImm.cs
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IOpCode32BReg.cs
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IOpCode32Mem.cs
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IOpCode32MemEx.cs
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IOpCode32MemMult.cs
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IOpCode32Simd.cs
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IOpCode32SimdImm.cs
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IOpCode.cs
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IOpCodeAlu.cs
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IOpCodeAluImm.cs
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IOpCodeAluRs.cs
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IOpCodeAluRx.cs
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IOpCodeBImm.cs
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IOpCodeCond.cs
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IOpCodeLit.cs
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IOpCodeSimd.cs
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OpCode32.cs
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OpCode32Alu.cs
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OpCode32AluBf.cs
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OpCode32AluImm16.cs
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OpCode32AluImm.cs
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OpCode32AluMla.cs
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OpCode32AluReg.cs
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OpCode32AluRsImm.cs
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OpCode32AluRsReg.cs
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OpCode32AluUmull.cs
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OpCode32AluUx.cs
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OpCode32BImm.cs
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OpCode32BReg.cs
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OpCode32Exception.cs
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OpCode32Mem.cs
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OpCode32MemImm8.cs
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OpCode32MemImm.cs
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OpCode32MemLdEx.cs
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OpCode32MemMult.cs
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OpCode32MemReg.cs
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OpCode32MemRsImm.cs
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OpCode32MemStEx.cs
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OpCode32MsrReg.cs
Implement MSR instruction for A32 (#2585)
2021-08-27 00:07:44 +02:00
OpCode32Sat16.cs
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OpCode32Sat.cs
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OpCode32Simd.cs
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OpCode32SimdBase.cs
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OpCode32SimdBinary.cs
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OpCode32SimdCmpZ.cs
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OpCode32SimdCvtFI.cs
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OpCode32SimdDupElem.cs
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OpCode32SimdDupGP.cs
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OpCode32SimdExt.cs
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OpCode32SimdImm44.cs
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OpCode32SimdImm.cs
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OpCode32SimdLong.cs
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OpCode32SimdMemImm.cs
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OpCode32SimdMemMult.cs
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OpCode32SimdMemPair.cs
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OpCode32SimdMemSingle.cs
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OpCode32SimdMovGp.cs
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OpCode32SimdMovGpDouble.cs
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OpCode32SimdMovGpElem.cs
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OpCode32SimdReg.cs
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OpCode32SimdRegElem.cs
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OpCode32SimdRegElemLong.cs
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OpCode32SimdRegLong.cs
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OpCode32SimdRegS.cs
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OpCode32SimdRegWide.cs
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OpCode32SimdRev.cs
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OpCode32SimdS.cs
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OpCode32SimdSel.cs
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OpCode32SimdShImm.cs
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OpCode32SimdShImmLong.cs
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OpCode32SimdShImmNarrow.cs
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OpCode32SimdSpecial.cs
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OpCode32SimdSqrte.cs
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OpCode32SimdTbl.cs
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OpCode32System.cs
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OpCode.cs
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OpCodeAdr.cs
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OpCodeAlu.cs
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OpCodeAluBinary.cs
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OpCodeAluImm.cs
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OpCodeAluRs.cs
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OpCodeAluRx.cs
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OpCodeBfm.cs
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OpCodeBImm.cs
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OpCodeBImmAl.cs
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OpCodeBImmCmp.cs
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OpCodeBImmCond.cs
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OpCodeBImmTest.cs
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OpCodeBReg.cs
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OpCodeCcmp.cs
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OpCodeCcmpImm.cs
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OpCodeCcmpReg.cs
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OpCodeCsel.cs
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OpCodeException.cs
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OpCodeMem.cs
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OpCodeMemEx.cs
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OpCodeMemImm.cs
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OpCodeMemLit.cs
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OpCodeMemPair.cs
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OpCodeMemReg.cs
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OpCodeMov.cs
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OpCodeMul.cs
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OpCodeSimd.cs
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OpCodeSimdCvt.cs
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OpCodeSimdExt.cs
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OpCodeSimdFcond.cs
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OpCodeSimdFmov.cs
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OpCodeSimdHelper.cs
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OpCodeSimdImm.cs
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OpCodeSimdIns.cs
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OpCodeSimdMemImm.cs
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OpCodeSimdMemLit.cs
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OpCodeSimdMemMs.cs
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OpCodeSimdMemPair.cs
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OpCodeSimdMemReg.cs
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OpCodeSimdMemSs.cs
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OpCodeSimdReg.cs
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OpCodeSimdRegElem.cs
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OpCodeSimdRegElemF.cs
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OpCodeSimdShImm.cs
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OpCodeSimdTbl.cs
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OpCodeSystem.cs
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OpCodeT16.cs
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OpCodeT16AluImm8.cs
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OpCodeT16BReg.cs
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OpCodeTable.cs
Implement MSR instruction for A32 (#2585)
2021-08-27 00:07:44 +02:00
RegisterSize.cs
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ShiftType.cs
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