mirror of
https://github.com/Ryujinx/Ryujinx.git
synced 2024-12-21 04:16:36 +00:00
c1bdf19061
* Implement ARM32 memory instructions: LDM, LDR, LDRB, LDRD, LDRH, LDRSB, LDRSH, STM, STR, STRB, STRD, STRH (immediate and register + immediate variants), implement CMP (immediate and register shifted by immediate variants) * Rename some opcode classes and flag masks for consistency * Fix a few suboptimal ARM32 codegen issues, only loads should be considered on decoder when checking if Rt == PC, and only NZCV flags should be considered for comparison optimizations * Take into account Rt2 for LDRD instructions aswell when checking if the instruction changes PC * Re-align arm32 instructions on the opcode table
57 lines
1.4 KiB
C#
57 lines
1.4 KiB
C#
using ChocolArm64.Instructions;
|
|
|
|
namespace ChocolArm64.Decoders
|
|
{
|
|
class OpCode32MemMult : OpCode32, IOpCode32MemMult
|
|
{
|
|
public int Rn { get; private set; }
|
|
|
|
public int RegisterMask { get; private set; }
|
|
public int Offset { get; private set; }
|
|
public int PostOffset { get; private set; }
|
|
|
|
public bool IsLoad { get; private set; }
|
|
|
|
public OpCode32MemMult(Inst inst, long position, int opCode) : base(inst, position, opCode)
|
|
{
|
|
Rn = (opCode >> 16) & 0xf;
|
|
|
|
bool isLoad = (opCode & (1 << 20)) != 0;
|
|
bool w = (opCode & (1 << 21)) != 0;
|
|
bool u = (opCode & (1 << 23)) != 0;
|
|
bool p = (opCode & (1 << 24)) != 0;
|
|
|
|
RegisterMask = opCode & 0xffff;
|
|
|
|
int regsSize = 0;
|
|
|
|
for (int index = 0; index < 16; index++)
|
|
{
|
|
regsSize += (RegisterMask >> index) & 1;
|
|
}
|
|
|
|
regsSize *= 4;
|
|
|
|
if (!u)
|
|
{
|
|
Offset -= regsSize;
|
|
}
|
|
|
|
if (u == p)
|
|
{
|
|
Offset += 4;
|
|
}
|
|
|
|
if (w)
|
|
{
|
|
PostOffset = u ? regsSize : -regsSize;
|
|
}
|
|
else
|
|
{
|
|
PostOffset = 0;
|
|
}
|
|
|
|
IsLoad = isLoad;
|
|
}
|
|
}
|
|
} |