ryujinx/ChocolArm64/Instruction
2018-04-04 16:36:07 -03:00
..
AInst.cs
AInstEmitAlu.cs Add Cls Instruction. (#67) 2018-03-23 22:06:05 -03:00
AInstEmitAluHelper.cs
AInstEmitBfm.cs
AInstEmitCcmp.cs
AInstEmitCsel.cs
AInstEmitException.cs Allow more than one process, free resources on process dispose, implement SvcExitThread 2018-03-12 01:14:12 -03:00
AInstEmitFlow.cs
AInstEmitHash.cs Remove unused function from CPU 2018-03-14 00:57:07 -03:00
AInstEmitMemory.cs
AInstEmitMemoryEx.cs
AInstEmitMemoryHelper.cs Allow to enable/disable memory checks even on release mode through the flag, return error for invalid addresses on SvcMap*Memory svcs, do not return error on SvcQueryMemory (instead, return reserved for the end of the address space), other minor tweaks 2018-03-10 20:39:16 -03:00
AInstEmitMove.cs
AInstEmitMul.cs
AInstEmitSimdArithmetic.cs Add FNEG (vector) instruction 2018-04-04 16:36:07 -03:00
AInstEmitSimdCmp.cs
AInstEmitSimdCvt.cs
AInstEmitSimdHelper.cs Fix EXT/Widening instruction carrying garbage values on some cases, fix ABD (it shouldn't accumulate, this is another variation of the instruction) 2018-03-30 17:37:31 -03:00
AInstEmitSimdLogical.cs Add BIT instruction 2018-03-30 16:46:00 -03:00
AInstEmitSimdMemory.cs
AInstEmitSimdMove.cs Fix EXT/Widening instruction carrying garbage values on some cases, fix ABD (it shouldn't accumulate, this is another variation of the instruction) 2018-03-30 17:37:31 -03:00
AInstEmitSimdShift.cs CPU fix for the cases using a Mask with shift = 0 2018-03-14 01:59:22 -03:00
AInstEmitSystem.cs Add pl:u stub, use higher precision on CNTPCT_EL0 register tick count 2018-03-13 21:24:32 -03:00
AInstEmitter.cs
ASoftFallback.cs Add Cls Instruction. (#67) 2018-03-23 22:06:05 -03:00