ryujinx/Ryujinx/Cpu
2018-02-15 01:32:25 -03:00
..
Decoder Emit CIL directly for more SIMD instructions, add UCVTF (vector, scalar) and UZP2, fix XTN (?) 2018-02-15 01:32:25 -03:00
Exceptions
Instruction Emit CIL directly for more SIMD instructions, add UCVTF (vector, scalar) and UZP2, fix XTN (?) 2018-02-15 01:32:25 -03:00
Memory Made initial implementation of the thread scheduler, refactor Svc to avoid passing many arguments 2018-02-13 23:43:08 -03:00
State
Translation Emit CIL directly for more SIMD instructions, add UCVTF (vector, scalar) and UZP2, fix XTN (?) 2018-02-15 01:32:25 -03:00
ABitUtils.cs
AOpCodeTable.cs Emit CIL directly for more SIMD instructions, add UCVTF (vector, scalar) and UZP2, fix XTN (?) 2018-02-15 01:32:25 -03:00
AOptimizations.cs
AThread.cs Made initial implementation of the thread scheduler, refactor Svc to avoid passing many arguments 2018-02-13 23:43:08 -03:00
ATranslatedSub.cs
ATranslator.cs