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ryujinx/ARMeilleure
History
LDj3SNuD 5a91efb525 Merge branch 'a32_tester_fpscr_followup' of https://github.com/LDj3SNuD/Ryujinx into a32_tester_fpscr_followup
2020-07-27 16:57:10 +02:00
..
CodeGen
Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (#1328)
2020-07-13 20:48:14 +10:00
Common
CodeGen Optimisations (LSRA and Translator) (#978)
2020-03-18 22:44:32 +11:00
Decoders
Implements some 32-bit instructions (VBIC, VTST, VSRA) (#1192)
2020-07-19 15:11:58 -03:00
Diagnostics
Add Profiled Persistent Translation Cache. (#769)
2020-06-16 20:28:02 +02:00
Instructions
Add Fpscr.Qc = 1 if sat. for Vqrshrn & Vqrshrun.
2020-07-27 16:56:59 +02:00
IntermediateRepresentation
Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli variants. (#1328)
2020-07-13 20:48:14 +10:00
Memory
Implement a new physical memory manager and replace DeviceMemory (#856)
2020-05-04 08:54:50 +10:00
State
Merge branch 'master' into a32_tester_fpscr_followup
2020-07-27 05:51:24 +02:00
Translation
Add Fpscr.Qc = 1 if sat. for Vqrshrn & Vqrshrun.
2020-07-27 16:56:59 +02:00
ARMeilleure.csproj
Add Profiled Persistent Translation Cache. (#769)
2020-06-16 20:28:02 +02:00
Optimizations.cs
Faster crc32 implementation (#1294)
2020-06-05 20:58:27 +10:00
Statistics.cs
Suppress warnings from fields never used or never assigned (CS0169 and CS0649) (#919)
2020-04-21 07:59:59 +10:00

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