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Add FMUL (scalar, by element) instruction; add FRECPE, FRECPS (scalar & vector) instructions. Add 5 simple tests. (#74)
* Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs * Update AInstEmitSimdHelper.cs * Update CpuTestSimdArithmetic.cs * Update AOpCodeTable.cs * Update AInstEmitSimdArithmetic.cs
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@ -224,6 +224,7 @@ namespace ChocolArm64
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Set("1001111010101111000000xxxxxxxxxx", AInstEmit.Fmov_Itof1, typeof(AOpCodeSimdCvt));
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Set("000111110x0xxxxx1xxxxxxxxxxxxxxx", AInstEmit.Fmsub_S, typeof(AOpCodeSimdReg));
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Set("000111100x1xxxxx000010xxxxxxxxxx", AInstEmit.Fmul_S, typeof(AOpCodeSimdReg));
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Set("010111111<<xxxxx1001x0xxxxxxxxxx", AInstEmit.Fmul_Se, typeof(AOpCodeSimdRegElemF));
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Set("0>1011100<1xxxxx110111xxxxxxxxxx", AInstEmit.Fmul_V, typeof(AOpCodeSimdReg));
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Set("0x0011111<<xxxxx1001x0xxxxxxxxxx", AInstEmit.Fmul_Ve, typeof(AOpCodeSimdRegElemF));
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Set("000111100x100001010000xxxxxxxxxx", AInstEmit.Fneg_S, typeof(AOpCodeSimd));
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@ -231,6 +232,10 @@ namespace ChocolArm64
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Set("000111110x1xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Fnmadd_S, typeof(AOpCodeSimdReg));
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Set("000111110x1xxxxx1xxxxxxxxxxxxxxx", AInstEmit.Fnmsub_S, typeof(AOpCodeSimdReg));
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Set("000111100x1xxxxx100010xxxxxxxxxx", AInstEmit.Fnmul_S, typeof(AOpCodeSimdReg));
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Set("010111101x100001110110xxxxxxxxxx", AInstEmit.Frecpe_S, typeof(AOpCodeSimd));
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Set("0>0011101<100001110110xxxxxxxxxx", AInstEmit.Frecpe_V, typeof(AOpCodeSimd));
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Set("010111100x1xxxxx111111xxxxxxxxxx", AInstEmit.Frecps_S, typeof(AOpCodeSimdReg));
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Set("0>0011100<1xxxxx111111xxxxxxxxxx", AInstEmit.Frecps_V, typeof(AOpCodeSimdReg));
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Set("000111100x100110010000xxxxxxxxxx", AInstEmit.Frinta_S, typeof(AOpCodeSimd));
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Set("0>1011100<100001100010xxxxxxxxxx", AInstEmit.Frinta_V, typeof(AOpCodeSimd));
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Set("000111100x100111110000xxxxxxxxxx", AInstEmit.Frinti_S, typeof(AOpCodeSimd));
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@ -256,6 +256,11 @@ namespace ChocolArm64.Instruction
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EmitScalarBinaryOpF(Context, () => Context.Emit(OpCodes.Mul));
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}
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public static void Fmul_Se(AILEmitterCtx Context)
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{
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EmitScalarBinaryOpByElemF(Context, () => Context.Emit(OpCodes.Mul));
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}
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public static void Fmul_V(AILEmitterCtx Context)
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{
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EmitVectorBinaryOpF(Context, () => Context.Emit(OpCodes.Mul));
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@ -324,6 +329,110 @@ namespace ChocolArm64.Instruction
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});
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}
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public static void Frecpe_S(AILEmitterCtx Context)
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{
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EmitFrecpe(Context, 0, Scalar: true);
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}
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public static void Frecpe_V(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int SizeF = Op.Size & 1;
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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for (int Index = 0; Index < Bytes >> SizeF + 2; Index++)
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{
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EmitFrecpe(Context, Index, Scalar: false);
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}
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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private static void EmitFrecpe(AILEmitterCtx Context, int Index, bool Scalar)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int SizeF = Op.Size & 1;
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if (SizeF == 0)
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{
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Context.EmitLdc_R4(1);
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}
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else /* if (SizeF == 1) */
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{
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Context.EmitLdc_R8(1);
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}
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EmitVectorExtractF(Context, Op.Rn, Index, SizeF);
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Context.Emit(OpCodes.Div);
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if (Scalar)
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{
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EmitVectorZeroAll(Context, Op.Rd);
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}
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EmitVectorInsertF(Context, Op.Rd, Index, SizeF);
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}
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public static void Frecps_S(AILEmitterCtx Context)
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{
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EmitFrecps(Context, 0, Scalar: true);
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}
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public static void Frecps_V(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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int SizeF = Op.Size & 1;
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int Bytes = Context.CurrOp.GetBitsCount() >> 3;
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for (int Index = 0; Index < Bytes >> SizeF + 2; Index++)
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{
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EmitFrecps(Context, Index, Scalar: false);
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}
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if (Op.RegisterSize == ARegisterSize.SIMD64)
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{
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EmitVectorZeroUpper(Context, Op.Rd);
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}
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}
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private static void EmitFrecps(AILEmitterCtx Context, int Index, bool Scalar)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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int SizeF = Op.Size & 1;
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if (SizeF == 0)
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{
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Context.EmitLdc_R4(2);
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}
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else /* if (SizeF == 1) */
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{
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Context.EmitLdc_R8(2);
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}
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EmitVectorExtractF(Context, Op.Rn, Index, SizeF);
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EmitVectorExtractF(Context, Op.Rm, Index, SizeF);
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Context.Emit(OpCodes.Mul);
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Context.Emit(OpCodes.Sub);
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if (Scalar)
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{
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EmitVectorZeroAll(Context, Op.Rd);
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}
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EmitVectorInsertF(Context, Op.Rd, Index, SizeF);
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}
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public static void Frinta_S(AILEmitterCtx Context)
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{
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AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
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@ -745,4 +854,4 @@ namespace ChocolArm64.Instruction
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EmitVectorWidenRnRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Mul));
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}
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}
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}
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}
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@ -120,6 +120,32 @@ namespace ChocolArm64.Instruction
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Context.EmitCall(MthdInfo);
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}
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public static void EmitScalarBinaryOpByElemF(AILEmitterCtx Context, Action Emit)
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{
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AOpCodeSimdRegElemF Op = (AOpCodeSimdRegElemF)Context.CurrOp;
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EmitScalarOpByElemF(Context, Emit, Op.Index, Ternary: false);
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}
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public static void EmitScalarOpByElemF(AILEmitterCtx Context, Action Emit, int Elem, bool Ternary)
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{
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AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
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int SizeF = Op.Size & 1;
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if (Ternary)
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{
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EmitVectorExtractF(Context, Op.Rd, 0, SizeF);
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}
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EmitVectorExtractF(Context, Op.Rn, 0, SizeF);
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EmitVectorExtractF(Context, Op.Rm, Elem, SizeF);
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Emit();
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EmitScalarSetF(Context, Op.Rd, SizeF);
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}
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public static void EmitScalarUnaryOpSx(AILEmitterCtx Context, Action Emit)
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{
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EmitScalarOp(Context, Emit, OperFlags.Rn, true);
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@ -724,4 +750,4 @@ namespace ChocolArm64.Instruction
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}
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}
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}
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}
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}
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@ -44,6 +44,53 @@ namespace Ryujinx.Tests.Cpu
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Assert.AreEqual(Result1, ThreadState.V0.X1);
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});
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}
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[Test, Description("fmul s6, s1, v0.s[2]")]
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public void Fmul_Se([Random(10)] float A, [Random(10)] float B)
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{
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AThreadState ThreadState = SingleOpcode(0x5F809826, V1: new AVec { S0 = A }, V0: new AVec { S2 = B });
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Assert.That(ThreadState.V6.S0, Is.EqualTo(A * B));
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}
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[Test, Description("frecpe v2.4s, v0.4s")]
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public void Frecpe_V([Random(100)] float A)
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{
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AThreadState ThreadState = SingleOpcode(0x4EA1D802, V0: new AVec { S0 = A, S1 = A, S2 = A, S3 = A });
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Assert.That(ThreadState.V2.S0, Is.EqualTo(1 / A));
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Assert.That(ThreadState.V2.S1, Is.EqualTo(1 / A));
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Assert.That(ThreadState.V2.S2, Is.EqualTo(1 / A));
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Assert.That(ThreadState.V2.S3, Is.EqualTo(1 / A));
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}
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[Test, Description("frecpe d0, d1")]
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public void Frecpe_S([Random(100)] double A)
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{
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AThreadState ThreadState = SingleOpcode(0x5EE1D820, V1: new AVec { D0 = A });
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Assert.That(ThreadState.V0.D0, Is.EqualTo(1 / A));
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}
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[Test, Description("frecps v4.4s, v2.4s, v0.4s")]
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public void Frecps_V([Random(10)] float A, [Random(10)] float B)
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{
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AThreadState ThreadState = SingleOpcode(0x4E20FC44, V2: new AVec { S0 = A, S1 = A, S2 = A, S3 = A },
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V0: new AVec { S0 = B, S1 = B, S2 = B, S3 = B });
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Assert.That(ThreadState.V4.S0, Is.EqualTo(2 - (A * B)));
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Assert.That(ThreadState.V4.S1, Is.EqualTo(2 - (A * B)));
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Assert.That(ThreadState.V4.S2, Is.EqualTo(2 - (A * B)));
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Assert.That(ThreadState.V4.S3, Is.EqualTo(2 - (A * B)));
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}
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[Test, Description("frecps d0, d1, d2")]
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public void Frecps_S([Random(10)] double A, [Random(10)] double B)
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{
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AThreadState ThreadState = SingleOpcode(0x5E62FC20, V1: new AVec { D0 = A }, V2: new AVec { D0 = B });
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Assert.That(ThreadState.V0.D0, Is.EqualTo(2 - (A * B)));
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}
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[TestCase(0x3FE66666u, false, 0x40000000u)]
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[TestCase(0x3F99999Au, false, 0x3F800000u)]
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