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https://github.com/Ryujinx/Ryujinx.git
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Implement Arm32 VSHLL and QADD16 instructions (#7301)
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ca59c3f499
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@ -746,6 +746,7 @@ namespace ARMeilleure.Decoders
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SetA32("<<<<01101000xxxxxxxxxxxxxx01xxxx", InstName.Pkh, InstEmit32.Pkh, OpCode32AluRsImm.Create);
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SetA32("<<<<01101000xxxxxxxxxxxxxx01xxxx", InstName.Pkh, InstEmit32.Pkh, OpCode32AluRsImm.Create);
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SetA32("11110101xx01xxxx1111xxxxxxxxxxxx", InstName.Pld, InstEmit32.Nop, OpCode32.Create);
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SetA32("11110101xx01xxxx1111xxxxxxxxxxxx", InstName.Pld, InstEmit32.Nop, OpCode32.Create);
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SetA32("11110111xx01xxxx1111xxxxxxx0xxxx", InstName.Pld, InstEmit32.Nop, OpCode32.Create);
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SetA32("11110111xx01xxxx1111xxxxxxx0xxxx", InstName.Pld, InstEmit32.Nop, OpCode32.Create);
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SetA32("<<<<01100010xxxxxxxx11110001xxxx", InstName.Qadd16, InstEmit32.Qadd16, OpCode32AluReg.Create);
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SetA32("<<<<011011111111xxxx11110011xxxx", InstName.Rbit, InstEmit32.Rbit, OpCode32AluReg.Create);
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SetA32("<<<<011011111111xxxx11110011xxxx", InstName.Rbit, InstEmit32.Rbit, OpCode32AluReg.Create);
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SetA32("<<<<011010111111xxxx11110011xxxx", InstName.Rev, InstEmit32.Rev, OpCode32AluReg.Create);
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SetA32("<<<<011010111111xxxx11110011xxxx", InstName.Rev, InstEmit32.Rev, OpCode32AluReg.Create);
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SetA32("<<<<011010111111xxxx11111011xxxx", InstName.Rev16, InstEmit32.Rev16, OpCode32AluReg.Create);
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SetA32("<<<<011010111111xxxx11111011xxxx", InstName.Rev16, InstEmit32.Rev16, OpCode32AluReg.Create);
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@ -1034,6 +1035,7 @@ namespace ARMeilleure.Decoders
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SetAsimd("111100101x>>>xxxxxxx0101>xx1xxxx", InstName.Vshl, InstEmit32.Vshl, OpCode32SimdShImm.Create, OpCode32SimdShImm.CreateT32);
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SetAsimd("111100101x>>>xxxxxxx0101>xx1xxxx", InstName.Vshl, InstEmit32.Vshl, OpCode32SimdShImm.Create, OpCode32SimdShImm.CreateT32);
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SetAsimd("1111001x0xxxxxxxxxxx0100xxx0xxxx", InstName.Vshl, InstEmit32.Vshl_I, OpCode32SimdReg.Create, OpCode32SimdReg.CreateT32);
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SetAsimd("1111001x0xxxxxxxxxxx0100xxx0xxxx", InstName.Vshl, InstEmit32.Vshl_I, OpCode32SimdReg.Create, OpCode32SimdReg.CreateT32);
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SetAsimd("1111001x1x>>>xxxxxxx101000x1xxxx", InstName.Vshll, InstEmit32.Vshll, OpCode32SimdShImmLong.Create, OpCode32SimdShImmLong.CreateT32); // A1 encoding.
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SetAsimd("1111001x1x>>>xxxxxxx101000x1xxxx", InstName.Vshll, InstEmit32.Vshll, OpCode32SimdShImmLong.Create, OpCode32SimdShImmLong.CreateT32); // A1 encoding.
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SetAsimd("111100111x11<<10xxxx001100x0xxxx", InstName.Vshll, InstEmit32.Vshll2, OpCode32SimdMovn.Create, OpCode32SimdMovn.CreateT32); // A2 encoding.
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SetAsimd("1111001x1x>>>xxxxxxx0000>xx1xxxx", InstName.Vshr, InstEmit32.Vshr, OpCode32SimdShImm.Create, OpCode32SimdShImm.CreateT32);
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SetAsimd("1111001x1x>>>xxxxxxx0000>xx1xxxx", InstName.Vshr, InstEmit32.Vshr, OpCode32SimdShImm.Create, OpCode32SimdShImm.CreateT32);
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SetAsimd("111100101x>>>xxxxxxx100000x1xxx0", InstName.Vshrn, InstEmit32.Vshrn, OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32);
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SetAsimd("111100101x>>>xxxxxxx100000x1xxx0", InstName.Vshrn, InstEmit32.Vshrn, OpCode32SimdShImmNarrow.Create, OpCode32SimdShImmNarrow.CreateT32);
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SetAsimd("111100111x>>>xxxxxxx0101>xx1xxxx", InstName.Vsli, InstEmit32.Vsli_I, OpCode32SimdShImm.Create, OpCode32SimdShImm.CreateT32);
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SetAsimd("111100111x>>>xxxxxxx0101>xx1xxxx", InstName.Vsli, InstEmit32.Vsli_I, OpCode32SimdShImm.Create, OpCode32SimdShImm.CreateT32);
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@ -292,6 +292,16 @@ namespace ARMeilleure.Instructions
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EmitAluStore(context, res);
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EmitAluStore(context, res);
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}
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}
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public static void Qadd16(ArmEmitterContext context)
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{
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OpCode32AluReg op = (OpCode32AluReg)context.CurrOp;
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SetIntA32(context, op.Rd, EmitSigned16BitPair(context, GetIntA32(context, op.Rn), GetIntA32(context, op.Rm), (d, n, m) =>
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{
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EmitSaturateRange(context, d, context.Add(n, m), 16, unsigned: false, setQ: false);
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}));
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}
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public static void Rbit(ArmEmitterContext context)
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public static void Rbit(ArmEmitterContext context)
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{
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{
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Operand m = GetAluM(context);
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Operand m = GetAluM(context);
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@ -976,6 +986,94 @@ namespace ARMeilleure.Instructions
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}
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}
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}
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}
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private static void EmitSaturateRange(ArmEmitterContext context, Operand result, Operand value, uint saturateTo, bool unsigned, bool setQ = true)
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{
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Debug.Assert(saturateTo <= 32);
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Debug.Assert(!unsigned || saturateTo < 32);
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if (!unsigned && saturateTo == 32)
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{
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// No saturation possible for this case.
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context.Copy(result, value);
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return;
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}
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else if (saturateTo == 0)
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{
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// Result is always zero if we saturate 0 bits.
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context.Copy(result, Const(0));
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return;
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}
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Operand satValue;
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if (unsigned)
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{
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// Negative values always saturate (to zero).
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// So we must always ignore the sign bit when masking, so that the truncated value will differ from the original one.
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satValue = context.BitwiseAnd(value, Const((int)(uint.MaxValue >> (32 - (int)saturateTo))));
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}
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else
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{
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satValue = context.ShiftLeft(value, Const(32 - (int)saturateTo));
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satValue = context.ShiftRightSI(satValue, Const(32 - (int)saturateTo));
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}
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// If the result is 0, the values are equal and we don't need saturation.
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Operand lblNoSat = Label();
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context.BranchIfFalse(lblNoSat, context.Subtract(value, satValue));
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// Saturate and set Q flag.
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if (unsigned)
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{
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if (saturateTo == 31)
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{
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// Only saturation case possible when going from 32 bits signed to 32 or 31 bits unsigned
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// is when the signed input is negative, as all positive values are representable on a 31 bits range.
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satValue = Const(0);
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}
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else
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{
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satValue = context.ShiftRightSI(value, Const(31));
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satValue = context.BitwiseNot(satValue);
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satValue = context.ShiftRightUI(satValue, Const(32 - (int)saturateTo));
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}
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}
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else
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{
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if (saturateTo == 1)
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{
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satValue = context.ShiftRightSI(value, Const(31));
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}
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else
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{
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satValue = Const(uint.MaxValue >> (33 - (int)saturateTo));
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satValue = context.BitwiseExclusiveOr(satValue, context.ShiftRightSI(value, Const(31)));
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}
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}
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if (setQ)
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{
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SetFlag(context, PState.QFlag, Const(1));
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}
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context.Copy(result, satValue);
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Operand lblExit = Label();
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context.Branch(lblExit);
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context.MarkLabel(lblNoSat);
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context.Copy(result, value);
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context.MarkLabel(lblExit);
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}
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private static void EmitSaturateUqadd(ArmEmitterContext context, Operand result, Operand value, uint saturateTo)
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private static void EmitSaturateUqadd(ArmEmitterContext context, Operand result, Operand value, uint saturateTo)
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{
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{
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Debug.Assert(saturateTo <= 32);
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Debug.Assert(saturateTo <= 32);
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@ -1053,6 +1151,21 @@ namespace ARMeilleure.Instructions
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context.MarkLabel(lblExit);
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context.MarkLabel(lblExit);
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}
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}
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private static Operand EmitSigned16BitPair(ArmEmitterContext context, Operand rn, Operand rm, Action<Operand, Operand, Operand> elementAction)
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{
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Operand tempD = context.AllocateLocal(OperandType.I32);
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Operand tempN = context.SignExtend16(OperandType.I32, rn);
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Operand tempM = context.SignExtend16(OperandType.I32, rm);
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elementAction(tempD, tempN, tempM);
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Operand tempD2 = context.ZeroExtend16(OperandType.I32, tempD);
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tempN = context.ShiftRightSI(rn, Const(16));
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tempM = context.ShiftRightSI(rm, Const(16));
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elementAction(tempD, tempN, tempM);
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return context.BitwiseOr(tempD2, context.ShiftLeft(tempD, Const(16)));
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}
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private static Operand EmitUnsigned16BitPair(ArmEmitterContext context, Operand rn, Operand rm, Action<Operand, Operand, Operand> elementAction)
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private static Operand EmitUnsigned16BitPair(ArmEmitterContext context, Operand rn, Operand rm, Action<Operand, Operand, Operand> elementAction)
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{
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{
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Operand tempD = context.AllocateLocal(OperandType.I32);
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Operand tempD = context.AllocateLocal(OperandType.I32);
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@ -106,6 +106,38 @@ namespace ARMeilleure.Instructions
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context.Copy(GetVecA32(op.Qd), res);
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context.Copy(GetVecA32(op.Qd), res);
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}
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}
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public static void Vshll2(ArmEmitterContext context)
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{
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OpCode32Simd op = (OpCode32Simd)context.CurrOp;
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Operand res = context.VectorZero();
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int elems = op.GetBytesCount() >> op.Size;
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for (int index = 0; index < elems; index++)
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{
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Operand me = EmitVectorExtract32(context, op.Qm, op.Im + index, op.Size, !op.U);
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if (op.Size == 2)
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{
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if (op.U)
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{
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me = context.ZeroExtend32(OperandType.I64, me);
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}
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else
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{
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me = context.SignExtend32(OperandType.I64, me);
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}
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}
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me = context.ShiftLeft(me, Const(8 << op.Size));
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res = EmitVectorInsert(context, res, me, index, op.Size + 1);
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}
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context.Copy(GetVecA32(op.Qd), res);
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}
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public static void Vshr(ArmEmitterContext context)
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public static void Vshr(ArmEmitterContext context)
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{
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{
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OpCode32SimdShImm op = (OpCode32SimdShImm)context.CurrOp;
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OpCode32SimdShImm op = (OpCode32SimdShImm)context.CurrOp;
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@ -527,6 +527,7 @@ namespace ARMeilleure.Instructions
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Pld,
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Pld,
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Pop,
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Pop,
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Push,
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Push,
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Qadd16,
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Rev,
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Rev,
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Revsh,
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Revsh,
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Rsb,
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Rsb,
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@ -29,6 +29,7 @@ namespace Ryujinx.Tests.Cpu
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{
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{
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return new[]
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return new[]
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{
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{
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0xe6200f10u, // QADD16 R0, R0, R0
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0xe6600f10u, // UQADD16 R0, R0, R0
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0xe6600f10u, // UQADD16 R0, R0, R0
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0xe6600f70u, // UQSUB16 R0, R0, R0
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0xe6600f70u, // UQSUB16 R0, R0, R0
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};
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};
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@ -328,6 +328,29 @@ namespace Ryujinx.Tests.Cpu
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CompareAgainstUnicorn();
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CompareAgainstUnicorn();
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}
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}
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[Test, Pairwise, Description("VSHLL.<size> {<Vd>}, <Vm>, #<imm>")]
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public void Vshll([Values(0u, 2u)] uint rd,
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[Values(1u, 0u)] uint rm,
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[Values(0u, 1u, 2u)] uint size,
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[Random(RndCnt)] ulong z,
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[Random(RndCnt)] ulong a,
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[Random(RndCnt)] ulong b)
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{
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uint opcode = 0xf3b20300u; // VSHLL.I8 Q0, D0, #8
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opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1);
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opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18);
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opcode |= size << 18;
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V128 v0 = MakeVectorE0E1(z, z);
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V128 v1 = MakeVectorE0E1(a, z);
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V128 v2 = MakeVectorE0E1(b, z);
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SingleOpcode(opcode, v0: v0, v1: v1, v2: v2);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("VSWP D0, D0")]
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[Test, Pairwise, Description("VSWP D0, D0")]
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public void Vswp([Values(0u, 1u)] uint rd,
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public void Vswp([Values(0u, 1u)] uint rd,
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[Values(0u, 1u)] uint rm,
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[Values(0u, 1u)] uint rm,
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